Phase-locked loop (PLL) circuits are used in both clock synthesis and clock recovery circuits. In clock synthesis circuits, a stable reference clock is used to produce an output clock generally of a frequency that is a multiple of the input clock frequency. In clock recovery circuits a data stream, usually Non-Return-to-Zero (NRZ) type, is the input and the clock associated with this input data stream is extracted by the PLL circuit and output.
FIG. 1 shows the block diagram of a phase-locked loop (PLL) consisting of a phase detector 10, a charge pump 12, a loop filter 14, a Voltage-Controlled Oscillator (VCO) 16 and a divide-by-N feedback 18. The phase detector is a key block of the PLL that affects locking properties such as acquisition range and transient response, as well as the jitter performance.
A Phase-and-Frequency Detector (PFD) is widely used in clock synthesizer PLLs, also known as CSUs (Clock Synthesis Units). On the other hand, a Hogge phase detector is an attractive choice for high-speed clock and data recovery circuits, also known as CRUs (Clock Recovery Units). A Hogge phase detector adjusts the edge of extracted clock to be at the center of the data eye and automatically provides built-in data retiming.
Phase-and-Frequency Detector (PFD)
In a conventional CSU based on a PFD and a divide-by-N feedback, the synthesized output frequency is N times the reference frequency: fOUT=N×fIN. FIG. 2a shows a typical PFD circuit combined with switched current sources 20 and 22 representing a charge pump, and a capacitor 24 representing a loop filter. The two inputs to the PFD are a reference clock (REFCLK) 26, and a feedback clock (FBCLK) 28. As shown in FIG. 2b, the rising edge of REFCLK sets the output UP, and the rising edge of FBCLK (i.e. VCO frequency divided by N) sets the output DOWN. Phase error is obtained by comparing the widths of UP and DOWN pulses. At ideal locked condition, the rising edges of REFCLK and FBCLK are perfectly aligned and net output of the charge pump is zero due to complete overlap of UP and DOWN pulses. If FBCLK moves with respect to REFCLK, the position of DOWN pulse moves accordingly and there will be an incremental (positive or negative) charge and voltage adjustment on the capacitor 24 that provides the control voltage VC to the VCO.
Combined with a charge pump, a PFD potentially suffers from a dead zone in its transfer characteristic, as shown by the solid line in FIG. 2c. The dead zone, which is due to inherent delay in turning on charge pump currents, directly translates to an equivalent peak-to-peak phase jitter in the PLL. To eliminate the dead zone, a larger delay τ is added in the reset path of the PFD. The resulting characteristic is shown with dashed line in FIG. 2c. Despite its popularity, this approach has some drawbacks that are typical of any asynchronous design. As the delay varies over process, temperature and power supply, if it becomes too small at some design corner, the dead zone or nonlinearity will appear there. On the other hand, the delay may not be made arbitrarily large, partly because it will eat into the dynamic range of the PFD from the two sides (see FIG. 2c). From a design point of view, the PFD circuit is not scalable, i.e. for a new frequency or process technology the delay element must be carefully readjusted.
Hogge Phase Detector
FIG. 3a shows the schematic of a Hogge phase detector. An attractive choice for high-speed clock and data recovery, the Hogge circuit adjusts the recovered clock edge at the center of data eye and automatically provides data retiming. For each input (data) transition, an UP pulse is generated at the output, followed by a DOWN pulse, causing a triangle-like activity on VC, i.e. the control voltage of the VCO. When there is no data transition, there is no activity on VC. Typical waveforms are shown in FIG. 3b. If the phase of Din varies (or jitters), the width of UP pulse and the corresponding charge varies, but DOWN pulse is fixed and provides a reference discharge. Thus, at the end of each UP-DOWN sequence there can be a net incremental voltage adjustment on VC. The Hogge phase detector has a linear characteristic with no dead zone as shown in FIG. 3c. However, the Hogge phase detector is not normally used in a low-jitter CSU since the periodic transitions of the reference clock make a triangular ripple always present on the VCO control line, corresponding to a small deterministic clock jitter.
The input dynamic range of a Hogge phase detector is in theory smaller than that of a PFD, i.e. ±π vs. ±2π. In practice the input dynamic range of a PFD is considerably narrowed from each side by the amount dedicated to reset pulse width (which depends on design margin, process, temperature, etc.). Also, the Hogge circuit as a phase detector (as opposed to a frequency detector) requires a frequency acquisition aid. For instance, some CRUs employ a PFD at start-up transient and switch to a Hogge phase detector after the frequency acquisition. In other designs, the center frequency of the VCO is swept by means of its control voltage (or current). In either case, a digital control circuit (a.k.a. digital wrapper) may supervise the transient process and switching action.
It is an object of the invention to realize a phase detector with improved jitter performance for clock synthesis units.
It is a further object of the invention to present a scalable design for the phase detector that does not rely on asynchronous elements.